1. Field of the Invention
The present invention relates to a MOS (Metal Oxide Silicon) semiconductor device and a method of manufacturing the same, and particularly a semiconductor device provided with wells having different depths as well as a method of manufacturing the same.
2. Description of the Background Art
In accordance with advances in design technology and process technology, it is now becoming possible to manufacture a high-density integrated circuit provided with a plurality of integrated circuits, which are the same as those manufactured independently of each other in the prior art, on a single chip. It is now becoming possible to produce a structure, in which a semiconductor device such as a DRAM (Dynamic Random Access Memory) as well as a high-density integrated logic circuit such as an MPU (Micro Processing Unit) are formed in a single chip. For manufacturing such integrated circuits, it is necessary to arrange within a single chip a plurality of MOS field-effect elements having different structures according to purposes.
A semiconductor device in which memory cells and a peripheral circuit are formed on a common substrate is disclosed, e.g., in Japanese Patent Laying-Open Nos. 4-212453 and 5-267606. These publications have disclosed semiconductor devices, in which a p-well region provided with memory cell transistors is surrounded by an n-region.
FIG. 50 is a cross section showing elements of a semiconductor device in the prior art. In FIG. 50, 101 indicate a p-type semiconductor substrate, 102 indicates an isolating and insulating film, 103 indicates an n-well and 104 indicates a p-well. According to this structure, in which p-well 104 of a memory cell part is surrounded by n-wells 103 and thereby is electrically isolated from the peripheral circuit part, the potential on p-well 104 can be determined independently, and n-wells 103 surrounding p-well 104 intercept electrons coming from p-type semiconductor substrate 101 so that soft error can be prevented.
For providing a deeper well, however, it is necessary to provide a wider region, which is not provided with a transistor, in the well end. In accordance with further miniaturization of the semiconductor integrated circuit, therefore, an isolation width and a width of the well are reduced, and the depth of the well is reduced. Thereby, the impurity concentration of the well increases, and the impurity concentration at the surface of the semiconductor substrate increases, resulting in a problem of deterioration of element characteristics such as increase in junction leak current. For suppressing the junction leak current, the impurity concentration of the well may be reduced. However, this results in a problem of increase in well resistance. Particularly in the memory cell region, the junction leak current deteriorates refresh characteristics.
The invention has been developed for overcoming the above problems, and it is an object to provide a semiconductor device, in which a semiconductor integrated circuit can be miniaturized while providing a memory cell region having improved refresh characteristics as well as a logic circuit having including shallow wells and therefore including miniaturized circuits capable of achieving required performances, and can achieve intended respective performances. It is also an object of the invention to provide a method of manufacturing such a semiconductor device.
It is an object of the invention to provide a semiconductor device, in which refresh characteristics are improved in a memory cell region, relatively shallow wells are employed in a logic circuit region for miniaturizing a circuit structure, and thereby performances required in the respective regions can be achieved in the miniaturized semiconductor integrated circuit having the memory cell region and the logic circuit region, as well as a method of manufacturing the semiconductor device.
For achieving the above object, a semiconductor device according to an aspect of the invention includes a semiconductor layer of a first conductivity type; a first impurity region of a second conductivity type formed at a main surface of the semiconductor layer and having a first impurity concentration peak; a second impurity region of the first conductivity type formed at the main surface of the semiconductor layer, located within a planar region provided with the first impurity region, and having a second impurity concentration peak at a smaller depth than the first impurity concentration peak; a third impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located within the planar region provided with the first impurity region, surrounding the second impurity region, and having a third impurity concentration peak at a smaller depth than the first impurity concentration peak; a fourth impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located in a region spaced from the first impurity region, and having a fourth impurity concentration peak; a fifth impurity region of the first conductivity type formed at the main surface of the semiconductor layer, located within a planar region provided with the fourth impurity region, and having a fifth impurity concentration peak at a smaller depth than the second and fourth impurity concentration peaks; a sixth impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located within a planar region provided with the fourth impurity region, surrounding the fifth impurity region and having a sixth impurity concentration peak at a smaller depth than the fourth impurity concentration peak; a first field-effect element of the second conductivity type formed at the main surface of the second impurity region; and a second field-effect element of the second conductivity type formed at the main surface of the fifth impurity region.
Owing to the above structure, a triple well structure can be employed for allowing setting of the substrate potential of the element independently of the semiconductor substrate while suppressing a junction leak current by the second impurity region, and allowing miniaturization by the fifth impurity region.
In the semiconductor device of the above aspect, the first impurity concentration peak and the fourth impurity concentration peak may be formed at the substantially equal depths from the main surface of the semiconductor layer, respectively. Thus, the first and fourth impurity regions may have the substantially same impurity concentration distributions in the direction of the substrate depth, whereby the semiconductor device having the triple well structure suitable to the multifunction configuration can be achieved through simple steps.
In this case, the first and third impurity regions may be spaced by a predetermined distance from each other in a direction of a depth determined from the main surface of the semiconductor layer, and the fourth and sixth impurity regions may be spaced by a predetermined distance from each other in the direction of the depth determined from the main surface of the semiconductor layer. According to the above structure, the semiconductor device having the triple well structure suitable to the multifunction configuration can be obtained while suppressing increase in number of steps.
According to an embodiment of the above aspect, the semiconductor device further includes a seventh impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located within a planar region provided with the first impurity region, surrounding the second impurity region, and having a seventh impurity concentration peak located shallower than the first impurity concentration peak and deeper than the third impurity concentration peak and being lower in concentration than the first and third impurity concentration peaks; and an eighth impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located in a region provided with the fourth impurity region, surrounding the fifth impurity region, and having an eighth impurity concentration peak located shallower than the fourth impurity concentration peak and deeper than the sixth impurity concentration peak and being lower in concentration than the fourth and sixth impurity concentration peaks.
According to this structure, since the first and fourth impurity regions have the same impurity concentration distributions in the direction of the substrate depth, the second or fifth impurity region can be electrically isolated from the semiconductor substrate with reliability. Therefore, the semiconductor device having the triple well structure suitable to the multifunction configuration can be obtained.
According to still another embodiment of the above aspect, the semiconductor device further includes a seventh impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located within a planar region provided with the first impurity region, surrounding the second impurity region with a predetermined distance therebetween, and having a seventh impurity concentration peak located shallower than the first impurity concentration peak and deeper than the third impurity concentration peak; and a third field-effect element of the first conductivity type formed in the third impurity region.
According to this structure, the impurity region of the conductivity type opposite to that of the substrate surrounds the second and fifth impurity regions for electrically isolating them from the substrate, and further the seventh and second impurity regions are formed in the spaced positions, respectively. Therefore, the third element can be formed even in the end of the third impurity region.
The fourth impurity concentration peak may be shallower than the first impurity concentration peak. According to this structure, the depths of the second and fifth impurity regions are utilized to change the depths of the impurity regions, which have the conductivity type opposite to that of the substrate and surround the second and fifth impurity regions, respectively. Thereby, further miniaturization can be achieved.
According to yet another embodiment, the semiconductor device of the above aspect further includes a ninth impurity region of the first conductivity type formed at the main surface of the semiconductor layer, located in a region different from the first and fourth impurity regions, and having a ninth impurity concentration peak at the substantially same depth as the second impurity concentration peak; a tenth impurity region of the first conductivity type formed at the main surface of the semiconductor layer, located in a region different from the first, fourth and ninth impurity regions, and having a tenth impurity concentration peak at the substantially same depth as the fifth impurity concentration peak; an eleventh impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located in a region different from the first, fourth, ninth and tenth impurity regions, and having an eleventh impurity concentration peak at the substantially same depth as the fifth impurity concentration peak; a twelfth impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located in a region different from the first, fourth, ninth, tenth and eleventh impurity regions, and having a twelfth impurity concentration peak at the substantially same depth as the second impurity concentration peak; a third field-effect element of the second conductivity type formed at the main surface of the ninth impurity region; a fourth field-effect element of the second conductivity type formed at the main surface of the tenth impurity region; a fifth field-effect element of the first conductivity type formed at the main surface of the eleventh impurity region; and a sixth field-effect element of the first conductivity type formed at the main surface of the twelfth impurity region.
According to the above structure, the concentration distribution of the well, which is not required to carry a fixed potential, is changed similarly to the other wells, if necessary. Therefore, elements corresponding to the required functions can be formed.
According to further another embodiment, the semiconductor device of the above aspect further includes a ninth impurity region of the first conductivity type formed at the main surface of the semiconductor layer, located in a region different from the first and fourth impurity regions, and having a ninth impurity concentration peak at the substantially same depth as the second impurity concentration peak; a tenth impurity region of the first conductivity type formed at the main surface of the semiconductor layer, located in a region different from the first, fourth and ninth impurity regions, and having a tenth impurity concentration peak at the substantially same depth as the fifth impurity concentration peak; an eleventh impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located in a region different from the first, fourth, ninth and tenth impurity regions, and having an eleventh impurity concentration peak; a third field-effect element of the second conductivity type formed at the main surface of the ninth impurity region; a fourth field-effect element of the second conductivity type formed at the main surface of the tenth impurity region; and a fifth field-effect element of the first conductivity type formed at the main surface of the eleventh impurity region, wherein the third, sixth and eleventh impurity concentration peaks are located at the substantially same depth as the fifth impurity concentration peak.
According to the above structure, since the third, sixth and eleventh impurity concentration peaks are present at the substantially same depth, the third, sixth and eleventh impurity regions can be formed at the same time.
In the semiconductor device of the above aspect, the third and sixth impurity concentration peaks may be shallower than the second impurity concentration peak and deeper than the fifth impurity concentration peak.
In this case, the concentration distributions are controlled so that the semiconductor device having a miniaturized structure and multiple functions can be achieved through simple steps.
In an embodiment, the semiconductor device further includes an impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located in a region different from the first and fourth regions, and having an impurity concentration peak at the substantially same depth as the third and sixth impurity concentration peaks; and an element of the first conductivity type formed in this impurity region.
According to this structure, the impurity regions of the conductivity type opposite to that of the substrate have the same concentration distributions in the region of the triple well structure and the region other than the triple well structure, and these concentration distributions are controlled so that these can be formed simultaneously.
According to a further embodiment, the semiconductor device of the above aspect further includes an impurity region of the first conductivity type formed at the main surface of the semiconductor layer, located in a region between the second and third impurity regions, and having an impurity concentration peak shallower than the second impurity concentration; and an element of the second conductivity type formed in this impurity region. According to this structure, since the impurity regions to be set to the same potential are formed as shallow as possible, further miniaturization can be achieved.
According to a further embodiment, the semiconductor device of the above aspect further includes another semiconductor layer disposed on another main surface of the semiconductor layer, and having a higher impurity concentration than the semiconductor layer. According to this structure, since the elements having multiple functions are disposed on the high-concentration substrate, latch-up in the deep portion of the well structure is suppressed.
A semiconductor device according to another aspect of the invention includes a semiconductor layer of a first conductivity type; a first impurity region of a second conductivity type formed at a main surface of the semiconductor layer and having a first impurity concentration peak; a second impurity region of the first conductivity type formed at the main surface of the semiconductor layer provided with the first impurity region, surrounded entirely by the first impurity region and having a second impurity concentration peak at a smaller depth than the first impurity concentration peak; a third impurity region of the first conductivity type formed at the main surface of the semiconductor layer, located in a region between the first and second impurity regions, surrounding the second impurity region, and having a third impurity concentration peak at a smaller depth than the second impurity concentration peak; and a first field-effect element of the second conductivity type formed at the main surface of the second impurity region.
Owing to the above structure, the third impurity region can reduce an electric field between the first and second impurity regions.
In the semiconductor device of the above aspect, the impurity region of the second conductivity type may not be present between the second and third impurity regions. Owing to this structure, the third impurity region can suppress the electric field between the first and second impurity regions.
According to an embodiment, the semiconductor device of the above aspect further includes a fourth impurity region of the first conductivity type formed at the main surface of the semiconductor layer, located in a region different from the first impurity region, and having a fourth impurity concentration peak at the substantially same depth as the second impurity concentration peak; a fifth impurity region of the first conductivity type formed at the main surface of the semiconductor layer, located in a region different from the first and fourth impurity regions, and having a fifth impurity concentration peak at a smaller depth than the second and fourth impurity concentration peaks; a sixth impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located in a region different from the first, fourth and fifth impurity regions, and having a sixth impurity concentration peak at the substantially same depth as the fifth impurity concentration peak; a seventh impurity region of the second conductivity type formed at the main surface of the semiconductor layer, located in a region different from the first, fourth and sixth impurity regions, and having a seventh impurity concentration peak at the substantially same depth as the fourth impurity concentration peak; a second field-effect element of the second conductivity type formed at the main surface of the fourth impurity region; a third field-effect element of the second conductivity type formed at the main surface of the fifth impurity region; a fourth field-effect element of the first conductivity type formed at the main surface of the sixth impurity region; a fifth field-effect element of the first conductivity type formed at the main surface of the seventh impurity region; and a capacitor connected to one of source/drain regions of the first element.
According to the above structure, since a memory cell transistor is formed in the second impurity region, the junction leak current can be suppressed.
According to an embodiment, the semiconductor device of the above aspect further includes another semiconductor layer disposed on another main surface of the semiconductor layer, and having a higher impurity concentration than the semiconductor layer. According to this structure, since elements having multiple functions are disposed on the high concentration substrate, latch-up in a deep portion of the well structure can be suppressed.
A method of manufacturing a semiconductor device according to the invention includes the steps of forming a first impurity region of a second conductivity type having a first impurity concentration peak at a main surface of a semiconductor layer of a first conductivity type; forming a second impurity region of the second conductivity type arranged at the main surface of the semiconductor layer, located in a region different from the first impurity region and having a second impurity concentration peak; forming a third impurity region of the first conductivity type arranged at the main surface of the semiconductor layer provided with the first impurity region, and having a third impurity concentration peak at a smaller depth than the first impurity concentration peak; forming a fourth impurity region of the first conductivity type formed at the main surface of the semiconductor layer provided with the second impurity region, and having a fourth impurity concentration peak at a smaller depth than the second impurity concentration peak; forming a fifth impurity region of the second conductivity type arranged at the main surface of the semiconductor layer provided with the first impurity region, and having a fifth impurity concentration peak at a smaller depth than the first and third impurity concentration peaks, and a sixth impurity region of the second conductivity type arranged at the main surface of the semiconductor layer provided with the second impurity region, surrounding the fourth impurity region and having the fifth impurity concentration peak; forming a first element of the second conductivity type at the main surface of the third impurity region; and forming a second element of the second conductivity type at the main surface of the fourth impurity region.
Owing to the above steps, a triple well structure can be employed for allowing setting of the substrate potential of the element independently of the semiconductor substrate, in which case the second impurity region can be deep and the fifth impurity region can be shallow. Further, the depths of the third and fourth impurity regions are utilized to change the depths of the impurity regions having the conductivity type opposite to that of the substrate and surrounding the third and fourth impurity regions, respectively.
According to an embodiment, the method of manufacturing the semiconductor device of the invention further includes the steps of forming a seventh impurity region of the second conductivity type arranged at the main surface of the semiconductor layer, located in a planar region provided with the first impurity region, surrounding the third impurity region, and having a seventh impurity concentration peak located shallower than the first impurity concentration peak and deeper than the fourth impurity concentration peak and being lower in concentration than the first and sixth impurity concentration peaks; and an eighth impurity region of the second conductivity type arranged at the main surface of the semiconductor layer, located in a region provided with the second impurity region, surrounding the fourth impurity region, and having the seventh impurity concentration peak.
According to the above steps, since the first and fourth impurity regions have the same impurity concentration distributions in the direction of the substrate depth, the second or fifth impurity region can be electrically isolated from the semiconductor substrate with reliability through simple steps. Therefore, the semiconductor device having the triple well structure suitable to the multifunction configuration can be obtained.
According to another embodiment of the method of manufacturing the semiconductor device of the invention, the step of forming the third impurity region includes the step of forming a ninth impurity region of the first conductivity type arranged at the main surface of the semiconductor layer, located in a region different from the first and second impurity regions, and having a ninth impurity concentration peak; the step of forming the fourth impurity region includes the step of forming a tenth impurity region of the first conductivity type arranged at the main surface of the semiconductor layer, located, in a region different from the first, second and ninth impurity regions, and having a tenth impurity concentration peak; and the step of forming the fifth and sixth impurity regions includes the step of forming an eleventh impurity region of the second conductivity type arranged at the main surface of the semiconductor layer, located in a region different from the first, second, ninth and tenth impurity regions, and having an eleventh impurity concentration peak.
According to the above steps, the concentration distribution of the well, which is not required to carry a fixed potential, can be changed similarly to the other wells, if necessary.
In the manufacturing method described above, the fifth, sixth and eleventh impurity concentration peaks may be disposed shallower than the third impurity concentration peak and deeper than the fourth impurity concentration peak.
The invention described above can achieve the following distinctive features.
According to the invention, the triple well structure is employed for setting the substrate potential of the element independently of the semiconductor substrate. In this case, the well provided with the element, which may suffer from a junction leak current, is formed at a large depth for achieving the function of the element, and the well provided with the element, which does not suffer from the junction leak current, is formed at a small depth for miniaturization. Thereby, the multiple functions and the miniaturization of the structure can be achieved at the same time. Independently of the depths of the wells provided with the elements, the impurity regions for electrically isolating the wells provided with the elements from the semiconductor substrates have the same impurity concentration distributions in the direction of depth of the substrate. Therefore, the semiconductor device having the multiple functions and the miniaturized structure can be achieved through simple steps.
The impurity region of the conductivity type opposite to that of the substrate surrounds the well for electrically isolating the well from the substrate, and this impurity region of the conductivity type opposite to that of the substrate has the impurity concentration distribution, which is changed for providing the well having the shallow impurity concentration peak. Therefore, the element can be formed even in the end of the well so that further miniaturization can be achieved.
In the semiconductor device having the triple well structure, the impurity region of the opposite conductivity type surrounding the shallow well is formed at a small depth, and the impurity region of the opposite conductivity type surrounding the deep well is formed at a large depth. Therefore, the semiconductor device having the multiple functions and the further miniaturized structure can be achieved.
The well which is not required to carry a fixed potential is configured to have a variable concentration distribution, if necessary. Therefore, both the multiple functions and the miniaturized structure can be simultaneously achieved in the semiconductor device.
A portion of the impurity region surrounding the well of the same conductivity type as the substrate in the triple well structure has the same concentration distribution as the impurity region, which is formed in another portion and is provided with the element. Therefore, these impurity regions can be formed at the same time, and the semiconductor device having the multifunctional structure and the miniaturized structure can be achieved through simple steps.
The impurity regions, which have the conductivity type opposite to that of the substrate, and are formed in the region of the triple well structure and the other region, have the same impurity concentration distributions which are controlled. Therefore, the semiconductor device having the multifunctional structure and the miniaturized structure can be achieved through simple steps.
In the semiconductor device having the triple well structure, wells of different depths are formed in the portion surrounded by the impurity region of the conductivity type opposite to that of the substrate, and these wells are formed as shallow as possible even in the case where the same potential is to be placed on these wells. Therefore, further miniaturization can be achieved.
In the semiconductor device, having the triple well structure, the memory transistor is formed in the well which is deep and has the same conductivity type as the substrate. Therefore, the junction leak current is suppressed, and the semiconductor device can have improved refresh characteristics.
In the semiconductor device having the triple well structure, the impurity region which has the same conductivity type as the substrate, and has the shallow impurity concentration peak is arranged between the well of the same conductivity type as the substrate and the impurity region of the opposite conductivity type surrounding this well. Therefore, the electric field between the well and the impurity region of the opposite conductivity type can be suppressed, and the junction leak current can be suppressed.
In the semiconductor device having the triple well structure, the memory cell transistor is formed in the deep well of the same conductivity type as the substrate. Therefore, it is possible to achieve the semiconductor device, in which the junction leak current is suppressed, and the refresh characteristics are improved.
Since the elements having multiple functions are disposed on the high-concentration substrate, latch-up in a deep portion of the well structure can be suppressed, and the semiconductor device having improved reliability can be achieved.
The triple well structure is employed for setting the substrate potential of the element independently of the semiconductor substrate. In this case, the well provided with the element, which may suffer from a junction leak current, is formed at a large depth for achieving the required function of the element, and the well provided with the element, which does not suffer from the junction leak current, is formed in the shallow well for achieving the miniaturization. Further, independently of the depths of the wells provided with the elements, the impurity regions for electrically isolating the respective wells provided with the elements from the semiconductor substrate have the same impurity concentration distributions in the direction of the substrate depth. Therefore, the semiconductor device in which the multifunctional structure and the miniaturized structure are simultaneously achieved can be obtained through simple steps.
Further, the impurity region of the conductivity type opposite to that of the substrate surrounds the well for electrically isolating the substrate from the well, and the portion of the impurity region provided with the element has the shallow impurity concentration peak. Therefore, the element can be formed even in the end of the above portion so that further miniaturization can be achieved.
In the semiconductor device having the triple well structure, the impurity region of the opposite conductivity type surrounding the shallow well can be formed at a small depth, and the impurity region of the opposite conductivity type surrounding the deep well can be formed at a large depth. Therefore, the semiconductor device can have the multiple functions and the further miniaturized structure.
In the triple well structure, a portion of the impurity region of the second conductivity type surrounding the well of the same conductivity type as the substrate has the same concentration distributions as the impurity region of the second conductivity type, which is formed in the other portion and is provided with the element. Therefore, these can be formed simultaneously. Accordingly, the semiconductor device having the multiple functions and the miniaturized structure can be achieved through simple steps.
In the semiconductor device having the triple well structure, the wells of different depths are formed in the portion surrounded by the impurity region of the conductivity type opposite to that of the substrate, and these wells are formed as shallow as possible even in the case where the same potential is to be placed thereon. Therefore, the semiconductor device can be further miniaturized.
In the semiconductor device having the triple well structure, the memory cell transistor is formed in the deep well of the same conductivity type as the substrate. Therefore, it is possible to provide the semiconductor device, in which the junction leak current is suppressed, and the refresh characteristics are improved.
In the semiconductor device having the triple well structure, the impurity region having the same conductivity type as the substrate and having the shallow impurity concentration peak is formed between the well of the same conductivity type as the substrate and the impurity region of the opposite conductivity type surrounding this well. Therefore, it is possible to suppress the electric field between the well and the impurity region of the opposite conductivity type, and it is possible to provide the semiconductor device in which the junction leak current is suppressed.
In the semiconductor device having the triple well structure, the memory cell transistor is formed in the deep well of the same conductivity type as the substrate. Therefore, it is possible to provide the semiconductor device in which the junction leak current is suppressed, and the refresh characteristics are improved.
Since epitaxial growth is executed on the surface of the high-concentration substrate, and the multifunctional elements are formed also on the epitaxial layer thus formed. Therefore, latch-up is likewise suppressed in a deep portion of the well structure, and the semiconductor device having improved reliability can be obtained.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.